Photonic integrated circuits are emerging as a promising complement to traditional CMOS circuits. This talk presents a mathematics-aided design methodology for photonic integrated circuits targeting digital computation. It bridges logic synthesis, physical design, and programmable photonic circuits through mathematical models and optimization techniques. Representative methods include harmonic-mean-based optical logic synthesis, timing-driven optical routing, and digital computation in programmable photonic circuits.

Jun-Wei Liang received the B.S. degree in Mathematics, the M.S. degree in Computer Science from the Graduate Institute of Electrical Engineering, and the Ph.D. degree in Electronic Design Automation from the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan.

His research interests include photonic design automation, photonic computing, optical logic synthesis, and mathematical modeling. His work explores how mathematical optimization and computer-aided design methodologies can enable scalable photonic systems for digital computation.

本場演講將邀請張孟凡特聘教授指導之博士生─游得奇同學，分享其於非揮發性記憶體內運算 (nvCIM) 晶片設計之研究與論文發表經驗，內容涵蓋基於磁阻式隨機存取記憶體 (STT-MRAM) 之近記憶體運算 (NMC) 與內記憶體運算 (IMC) 技術。此外，游同學亦將透過自身研究歷程，同與會者進行問答與交流，並鼓勵有志投入博士班研究之學生。

游得奇同學目前為國立清華大學電機工程學系博士班四年級學生，主要研究領域為內嵌式記憶體電路設計 (Embedded Memory Circuit Design) 與人工智慧記憶體內運算晶片設計 (CIM AI Chip Design)；目前已發表 5 篇第一作者論文 (1 篇 ISSCC、1 篇 VLSI、3 篇 JSSC)。

Recently, Transformer-based diffusion models (DMs) have emerged as powerful candidates for image generation, offering superior visual quality and model efficiency. However, the massive external memory access (EMA) driven by large parameter counts and two-sample classifier-free guidance (CFG) inference poses a critical bottleneck for edge deployment. Furthermore, preserving generation quality necessitates large floating-point on-chip memory.

In this talk, I will introduce our recent work, Tiamat, a memory- and energy-efficient processor for Transformer-based DM inference with intrinsic CFG support. Tiamat overcomes the critical challenges of EMA and on-chip memory through architecture innovation, algorithm-hardware co-design, and datapath optimization. Fabricated in 16-nm FinFET technology, Tiamat achieves a generation latency of 98-134 ms/step at 400 MHz and a generation energy of 75-99 mJ/step at 100 MHz, demonstrating its capability for real-time and energy-constrained scenarios. By leveraging the proposed techniques, Tiamat delivers a 3.90-7.48× faster generation time and a 1.16-2.22× lower system energy compared to state-of-the-art prior works.

Po-Yen Lu received the B.S. degree in electrical engineering from National Tsing Hua University (NTHU), Hsinchu, Taiwan, in 2023, where he is currently pursuing the M.S. degree.

His research interests include energy-efficient computing architecture design and digital VLSI system implementation for deep learning, computational photography, and computer vision.