| 發表編號 | 類別 | 論文標題 / 作者 / 所屬學校/公司 |
|---|---|---|
| P1-1 (33) | Analog & RF |
A High-Linearity 5×5 Micro-LED Driver with Internally Compensated Active R-2R DAC for Optoelectronic Integration
National Taiwan University
|
| P1-2 (49) | Analog & RF |
The Applications of FIR Quasi-Digital Current Control Technique on the 0.18μm Pseudo-LDO Regulator with Higher Efficiency, Fast Transient Response, and Extremely Absolutely-Stability on EMI Effects
1National Taipei University of Technology
2Asia Eastern University of Science and Technology
|
| P1-3 (70) | Analog & RF |
A Low-Power Floating-Gate Reconfigurable OTA-C Filter with Near-ZTC Temperature Compensation
1National Yang Ming Chiao Tung University
2National Taiwan University of Science and Technology
|
| P1-4 (96) | Analog & RF |
An Ultra-Low-Power RC Relaxation Oscillator with a Dual-mode Comparator
National Taiwan University
|
| P1-5 (109) | Analog & RF |
A Low-voltage Crystal-less Clock Generator
National United University
|
| P1-6 (113) | Analog & RF |
A 1.4-mW 12.8-GHz Fast-Locking Quadrature Phase-Locked Loop With a Mismatch-Suppressed Charge Pump for High-Speed Serial Links in 16-nm FinFET
1National Central University
2National Yang Ming Chiao Tung University
|
| P1-7 (141) | Analog & RF |
Magnetic Sensing System with Automatic Ripple Reduction and Variable Gain Readout Circuit
National Taipei University of Technology
|
| P1-8 (163) | Analog & RF |
A Threshold-Aware Time-Domain Capacitance-to-Digital Sensing System for Point-of-Care Detection of Cardiovascular Biomarkers
1National Yang Ming Chiao Tung University
2National Yang Ming Chiao Tung University
3National Tsing Hua University
4National Tsing Hua University
|
| P1-9 (186) | Analog & RF |
An FPGA-Based Hardware Acceleration Platform Design for Long-Read Sequence Alignment
National Taiwan University
|
| P1-10 (197) | Analog & RF |
A Compact Biomedical Readout System Integrating Potentiometric and Amperometric Measurements
National Yunlin University of Science and Technology
|
| P1-11 (258) | Analog & RF |
A 20 μW 18 nV/√𝐇𝐳 Noise Density Two-Stage CMOS Operational Transconductance Amplifier for Biomedical Monitoring Applications
National Central University
|
| P1-12 (264) | Analog & RF |
A Dynamic Comparator-based PUF with Low Energy in 16-nm FinFET and 90-nm CMOS
National Taiwan University of Science and Technology
|
| P1-13 (22) | Analog & RF |
Design of A 12-bit Successive-Approximation Register Analog-to-Digital Converter with Digital Error Correction
National Yunlin University of Science & Technology
|
| P1-14 (66) | Analog & RF |
Design of a 10-bit SAR ADC for Biomedical Applications Using a Reduced-Kickback Comparator and a Matching-Enhanced CDAC Layout
National Cheng Kung University
|
| P1-15 (73) | Analog & RF |
A 10-bit 10-GS/s 2x-TI DAC in 40-nm CMOS
National Taiwan University of Science and Technology
|
| P1-16 (118) | Analog & RF |
A 12-bit 12-MS/s FCPC-Assisted CR-SAR ADC with Fixed-Point Capacitor-Mismatch Calibration
1National Cheng-Kung University
2Novatek Microelectronics Corp
|
| P1-17 (147) | Analog & RF |
Design of a Low-Power Discrete-Time CIFB 2-1 Sigma-Delta MASH ADC with Digital Error Cancellation in 16-nm FinFET Technology
National Yunlin University of Science and Technology
|
| P1-18 (198) | Analog & RF |
A Third-Order Hybrid Error-Feedback Noise-Shaping SAR ADC Using Unity-Gain Buffer for Residue Transfer and In-Band Zero Placement
National Taiwan Normal University
|
| P1-19 (209) | Analog & RF |
A Partially Time-Interleaving Pipelined Noise-shaping SAR ADC with Amplifier Gain Error Shaping
National Cheng Kung University
|
| P1-20 (237) | Analog & RF |
A 78.7-dB-SNDR Discrete-Time Hybrid ADC Employing Flash-Assisted Incremental Delta-Sigma Modulation and Ring Amplifiers
Tamkang University
|
| P1-21 (8) | Digital & System |
Design and Implementation of a Programmable Maritime Satellite Digital Baseband Receiver
National Taiwan University of Science and Technology
|
| P1-22 (12) | Digital & System |
The Algorithm and Hardware Architecture Design for Canonical Polyadic Decomposition of Ill Conditioned Tensors
National Taiwan University of Science and Technology
|
| P1-23 (14) | Digital & System |
The Algorithm and VLSI Architecture Design of Low Complexity Tensor Ring Decomposition
National Taiwan University of Science and Technology
|
| P1-24 (20) | Digital & System |
The Impact of Misrouting Hardware Trojans on Eavesdropping Attacks in Network-on-Chip
National Yang Ming Chiao Tung University
|
| P1-25 (34) | Digital & System |
Holistic Circuit-Layout Co-Design of a 0.4-V Area-Efficient Clocked Storage Element with Enhanced OD Regularity in 16nm FinFET
Chaoyang University of Technology
|
| P1-26 (52) | Digital & System |
Eco-Secure-Net: A Communication-Efficient BNN-based Federated IDS for IoT Edge Devices with ASIC Implementation
National Taiwan Normal University
|
| P1-27 (60) | Digital & System |
FPGA Implementation of a Text-to-Image Network Based on GAN Architecture
National Yunlin University of Science and Technology
|
| P1-28 (97) | Digital & System |
An FPGA-based UAV System Design for Real-Time River Pollution Monitoring
National Changhua University of Education
|
| P1-29 (108) | Digital & System |
Low-Power Matrix Computation Accelerator Based on Distributed Arithmetic Multiplication Architecture
National Chiayi University
|
| P1-30 (112) | Digital & System |
Securing Medical Edge Accelerators Against On-Chip SRAM Faults via Ultra-Lightweight Spatial Redundancy
1Yuan Ze University
2National Taiwan Normal University
3Far Eastern Memorial Hospital
|
| P1-31 (31) | Digital & System |
Sparsity-Aware CNN Accelerator Co-Design
National Central University
|
| P1-32 (32) | Digital & System |
APC–FPGA Heterogeneous AI System for Multi-Model Table Tennis Officiating
National Central University
|
| P1-33 (40) | Digital & System |
HART: Hardware-Aligned Robust Training for Resource-Constrained Edge Device
1National Taiwan University
2Chung Yuan Christian University
3University of Lübeck
|
| P1-34 (54) | Digital & System |
A 2.21-W Parameter-Efficient CNN Hybrid Accelerator with Chebyshev-KAN Classifier on FPGA
1National Central University
2National Yang Ming Chiao Tung University
|
| P1-35 (62) | Digital & System |
HLS-based R2D2 Accelerator for Keypoint Detection and Local Feature Description
National Central University
|
| P1-36 (75) | Digital & System |
Hardware Architecture Design and Implementation of a Transformer for the LoFTR Feature Matching Model
National Sun Yat-sen University
|
| P1-37 (84) | Digital & System |
DPU-GAN: Deploying Text-to-Image GANs on FPGA Edge Platforms via DPU-Aligned Architecture
National Taiwan University of Science and Technology
|
| P1-38 (105) | Digital & System |
A Low-Power 1-D CNN Accelerator in 40-nm CMOS for Current-based Bearing Fault Diagnosis
National Chung Cheng University
|
| P1-39 (130) | Digital & System |
Design and Implementation of a Hybrid Hardware Accelerator Architecture for Convolutional Neural Network and Large Language Model
National Chung Hsing University
|
| P1-40 (132) | Digital & System |
Optimized Hardware Architecture and Implementation for Softmax Accelerator for LLMs
National Chung Hsing University
|
| P1-41 (25) | Digital & System |
A Multimodal Geometric Conditional Generation Framework Integrating Text-to-Bounding Box and Text-to-Pose: Vector Integration and Image Generation Preliminary Study
National Central University
|
| P1-42 (236) | Digital & System |
Subband-Aware and Dual-Branch Learning Algorithm for Ultra Lightweight ECG Denoising Autoencoder Design
1National Formosa University of Science and Technology,
2National Yunlin University of Science and Technology,
3Chaoyang University of Technology
|
| P1-43 (260) | Digital & System |
A Lightweight Compact Shortcut DAE with Simplified LSTM classifier Architecture for Edge ECG Denoising and Arrhythmia Recognition
1National Formosa University
2National Yunlin University of Science and Technology
|
| P1-44 (261) | Digital & System |
Design and Verification of Built-In Self-Test Circuits for Passive-Quenching SPAD Arrays
Feng Chia University
|
| P1-45 (265) | Digital & System |
Predictor Parameter Analysis and Hardware Architecture for CCSDS 123.0-B-2 Hyperspectral Image Compression
National Yunlin University of Science and Technology
|
| P1-46 (266) | Digital & System |
A Multi-Scale Dilated Convolutional Neural Network with Z-Score LMS for Edge-Based Wearable Heart Rate Estimation
1National Formosa University
2Chaoyang University of Technology
|
| P1-47 (5) | EDA & Testing |
High Accuracy Low Utilization Multi-Channel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multi-Dimensional Delay Array
National Taiwan University of Science and Technology
|
| P1-48 (51) | EDA & Testing |
Enhancing Machine Learning Resistance of Arbiter PUFs via FPGA-Aware Placement: A Study of Delay Correlation and Learnability
National Sun Yat-sen University
|
| P1-49 (128) | EDA & Testing |
Stealthy Aging Trojans in Delay Locking Circuits via Path Delay Balancing
National Central University
|
| P1-50 (149) | EDA & Testing |
Reliability Enhancement for 3D-DRAM by DQS Timing Calibration to Tolerate TSV Delay Variations
National Tsing Hua University
|
| P1-51 (9) | EDA & Testing |
Routing-Aware Simulated Annealing for Macro Placement Repair: Reopening SA with a Geometric Pre-Filter
Chung Yuan Christian University
|
| P1-52 (15) | EDA & Testing |
Phantom-Exit Congestion Optimization and Automatic QPO/SA Selection for an AI-Assisted Interactive Macro P&R Tool
Chung Yuan Christian University
|
| P1-53 (16) | EDA & Testing |
Study of GNN-Augmented Macro Placement Repair Compared to Geometric Pre-Filtering
Chung Yuan Christian University
|
| P1-54 (58) | EDA & Testing |
EM-Aware Placement for RF Analog Blocks on 28 nm 5G n78
Chung Yuan Christian University
|
| P1-55 (59) | EDA & Testing |
Phantom-Exit Negotiated Routing and Layer-Stack-Aware Sign-Off for RF Analog Blocks on 28 nm 5G n78
Chung Yuan Christian University
|
| P1-56 (10) | Emerging Technologies |
The CMOS Heavily Doped p+-Substrate with Negative Bias of Micromachined Magnetized Plasmonic Material Substrate on the Applications of the Plasmonic CMOS Bandgap Voltage Reference by Using the Technology of 0.18-µm CMOS Process in Theoretical
1National Taipei University of Technology
2Asia Eastern University of Science and Technology
|
| P1-57 (11) | Emerging Technologies |
The Polyphase Surface Processing Modification of Silicon Semiconductor Materials by Radio Frequency Produced Plasma at One Atmospheric Pressure
1National Taipei University of Technology
2Asia Eastern University of Science and Technology
|
| P1-58 (106) | Emerging Technologies |
A Q8.8 Fixed-Point VLSI Accelerator for Simulated Quantum Annealing with LUT-Based Nonlinear Function Units
National Taipei University
|
| P1-59 (222) | Emerging Technologies |
An Edge AI Driver Monitoring System Using DPU-Accelerated ResNet-18 on AMD KV260
National United University
|
| P1-60 (253) | Emerging Technologies |
YOLOV4 Pruning with Learn Gates & BN and Channel Interdependence Learning
National Cheng Kung University
|
| 發表編號 | 類別 | 論文標題 / 作者 / 所屬學校/公司 |
|---|---|---|
| P2-1 (18) | Analog & RF |
Cost-Saving and High Efficiency DC Power Transmission Line with HFSS and ADS Tools on Energy-Saving Techniques
1National Taipei University of Technology
2Asia Eastern University of Science and Technology
|
| P2-2 (26) | Analog & RF |
Analysis And Research On A Dual-Mode Power Management Chip Applied To High-Speed Memory
Chang Gung University
|
| P2-3 (28) | Analog & RF |
The Applications of FIR Quasi-Digital Voltage Control Technique on the 0.18μm Embedded Buck Converter with Output Line-Dropped Compensation Ability, and Extremely Fast Stable Transient Response on EMI Effects
1National Taipei University of Technology
2Asia Eastern University of Science and Technology
|
| P2-4 (79) | Analog & RF |
A Digital Buck Converter With Online Two-step Compensator Auto-tuning Mechanism
National Cheng Kung University
|
| P2-5 (88) | Analog & RF |
A Three-Stage Adaptive Gate Driver with Gate Sensing for SiC Power Device Turn-ON Optimization
National Taipei University of Technology
|
| P2-6 (200) | Analog & RF |
A High-Efficiency Buck Converter Supporting Large Dynamic Loads for AIoT Applications
1National Taipei University of Technology
2Lunghwa Univ. of Science and Technology
|
| P2-7 (206) | Analog & RF |
A Current-Mode Buck Converter with Transient Acceleration Circuit and Low-IQ Comparator
1National Taipei University of Technology
2National Taipei University of Technology
3Lunghwa Univ. of Science and Technology
|
| P2-8 (249) | Analog & RF |
A Buck Converter with Capacitor Current Inverse-Charge Constant On-Time Control
1National Taipei University of Technology
2Lunghwa Univ. of Science and Technology
|
| P2-9 (250) | Analog & RF |
An Adaptive On-Time Controlled Buck Converter with Load-Sensing Technique Achieving DCM Constant Output Ripple
1National Taipei University of Technology
2Lunghwa Univ. of Science and Technology
|
| P2-10 (270) | Analog & RF |
A Constant-On-Time Controlled Buck Converter with Integrated Protection and Zero-Current Detection
1National Taipei University of Technology
2Lunghwa Univ. of Science and Technology
|
| P2-11 (29) | Analog & RF |
Design and Implementation of High-Speed Avalanche Photodiode Measurement System Based on High-Voltage BCD Technology
National Yunlin University of Science & Technology
|
| P2-12 (67) | Analog & RF |
Half-Rate Reference-less Clock and Data Recovery for Optical Receivers in 65-nm CMOS
National Tsing Hua University
|
| P2-13 (68) | Analog & RF |
Design of a High-Performance Millimeter-Wave Receiver Front-End for 5G Communications
National Tsing Hua University
|
| P2-14 (99) | Analog & RF |
5GHz Phase-Locked Loop with Power-Improved Charge Pump
National Sun Yat-sen University
|
| P2-15 (111) | Analog & RF |
RF-ESD Co-Design of a High-Speed TIA and Bypass Circuit for Optical Receiver Front-Ends
National Yang Ming Chiao Tung University
|
| P2-16 (123) | Analog & RF |
A 20-Gb/s Continuous-Time Linear Equalizer with Feedforward Frequency Compensation in 40-nm CMOS
Yuan Ze University
|
| P2-17 (152) | Analog & RF |
Design of 2-turn 8-Shaped Inductors Used in VCO
1Ming Chi University of Technology
2National Taiwan University of Science and Technology
|
| P2-18 (184) | Analog & RF |
A Low-Power Harmonic-Resilient Mixer-First Receiver Using Third-Harmonic N-Path Mixing
National Cheng Kung University
|
| P2-19 (227) | Analog & RF |
An SSC Tracking Aid for Dual-Loop Digital CDRs
National Tsing Hua University
|
| P2-20 (120) | Digital & System |
Fully-Digital, ROM-less Sine and Gaussian Wave Generator with Linear Approximation and Error Correction
National Taiwan University of Science and Technology
|
| P2-21 (158) | Digital & System |
Hardware-Aware Image Resampling for FPGA-Based UAV Localization with Parameter-Guided ORB Matching
National Tsing Hua University
|
| P2-22 (174) | Digital & System |
Low-Power Approximate Computing Circuit Design for Fast Image Processing
Tunghai University
|
| P2-23 (203) | Digital & System |
A Region-Based Hop-to-Hop Topological Validation for Securing NoC Multicast
National Yang Ming Chiao Tung University
|
| P2-24 (208) | Digital & System |
A Compression-Aware Event Transformer Accelerator with Sparse Feature Transfer for Airborne Edge Perception
National Taiwan University of Science and Technology
|
| P2-25 (212) | Digital & System |
Adaptive Tensor Compression and Memory Offloading for Reliable and Efficient LLM Training
National Taiwan University of Science and Technology
|
| P2-26 (223) | Digital & System |
Design Space Exploration of a BRAM-Less Sobel Accelerator on Resource-Constrained FPGAs Using HLS
National United University
|
| P2-27 (137) | Digital & System |
A Group-Wise Sign-Remapped Partial-Product Scheme for SRAM-DCIM MACs
1National Sun Yat-sen University
2National Central University
|
| P2-28 (156) | Digital & System |
Stride–NMS Co-Design for Vision Transformer Hotspot Detection: A Diagnostic Study on the Precision Bottleneck
Chung Yuan Christian University
|
| P2-29 (175) | Digital & System |
A Heterogeneous System for Event-Based Video Reconstruction Using Hybrid-EVSNN
National Central University
|
| P2-30 (183) | Digital & System |
Design and FPGA Implementation of an Ultra-lightweight Ternary-Weight YOLO Inference Processor
National Taiwan University
|
| P2-31 (194) | Digital & System |
Layer-wise Mixed-Precision Quantization with HLS Pragma Co-Optimization for Resource-Constrained FPGAs: A Case Study on PYNQ-Z2
National Yunlin University
|
| P2-32 (210) | Digital & System |
Design and Implementation of a Low-Bit Inference Acceleration Processor for Large Language Models Based on Transformers and State-Space Models
National Taiwan University
|
| P2-33 (218) | Digital & System |
Unsupervised Reinforcement STDP Learning Methodology via Spike-based Intrinsic Reward
National Yang Ming Chiao Tung University
|
| P2-34 (220) | Digital & System |
Real-Time Medical Waste Classification Using Convolutional Neural Networks with Hardware Acceleration
National Central University
|
| P2-35 (239) | Digital & System |
Permutation-State Sparse-Delta Annealing for CIM-Compatible TSP Acceleration
National Yang Ming Chiao Tung University
|
| P2-36 (245) | Digital & System |
FPGA-Based Acceleration of Vision Transformers with Quantization and Token Reduction
National Yang Ming Chiao Tung University
|
| P2-37 (247) | Digital & System |
A 32x8 bits Fast-Access Static Random Access Memory Array Circuit with Dual-Output Functionality
National Taiwan University
|
| P2-38 (251) | Digital & System |
A Study of Lightweight CNN and Model Compression for Wafer Defect Classification on Resource-Constrained FPGA
National Changhua University of Education
|
| P2-39 (271) | Digital & System |
Design and Implementation of an Offline Infant Safety Monitoring System for Outdoor Scenarios
National Central University
|
| P2-40 (272) | Digital & System |
Smooth Exponent Optimization for Hardware-Friendly Post-Training Quantization
National Cheng Kung University
|
| P2-41 (277) | Digital & System |
An Efficient Hardware Architecture for Rotary Position Embedding with Extensible Variant Support
National Sun Yat-sen University
|
| P2-42 (257) | EDA & Testing |
A Test Data Compression Technique Using Geometric Shape Mapping
1Amador Valley High School
2Yuan Ze University
|
| P2-43 (269) | EDA & Testing |
High-Performance APB Transaction Error Detection via Efficient VCD Waveform Processing
National Central University
|
| P2-44 (283) | EDA & Testing |
A Data-Driven Hybrid Bucketing Framework for Automated RTL Regression Failure Triage
Yuan Ze University
|
| P2-45 (284) | EDA & Testing |
Residual-Driven Adaptive Test Pattern Generation
Tamkang University
|
| P2-46 (285) | EDA & Testing |
SAEG-LinUCB: A Contextual-Bandit Framework for Hierarchical ATPG Strategy and Hardware Scheduling
Tamkang University
|
| P2-47 (91) | EDA & Testing |
Learning-Based Temperature Scheduling for Simulated Annealing in VLSI CAD
National Yang Ming Chiao Tung University
|
| P2-48 (100) | EDA & Testing |
A Single-Port SRAM Compiler for ASAP7 PDK
Yuan Ze University
|
| P2-49 (101) | EDA & Testing |
LSAU-Net: A Layer-Scalable Attention U-Net for Fast Steady-State Thermal Prediction in 3D ICs
National Yang Ming Chiao Tung University
|
| P2-50 (103) | EDA & Testing |
Efficient Thermal Simulation for 3D-Stacked ICs Considering Lateral Heat Spreading and Structural Heterogeneity
National Yang Ming Chiao Tung University
|
| P2-51 (114) | EDA & Testing |
Viability of LLM-Based Soft Block Floorplanning
Yuan Ze University
|
| P2-52 (131) | EDA & Testing |
PG-GNN: Physics-Guided Graph Neural Network for Fast and Accurate Cell Timing Library Characterization
National Yang Ming Chiao Tung University
|
| P2-53 (154) | EDA & Testing |
SPICE Model for ESD Protection Capability of 1200 V SiC MOSFET
1National Taiwan University
2SiCEV Electronics Co., Ltd
|
| P2-54 (160) | EDA & Testing |
ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging
National Yang Ming Chiao Tung University
|
| P2-55 (172) | EDA & Testing |
OPC+: GPU-Accelerated Lithography Simulation with Contour-Based Calibration and Unified Inverse Mask Optimization
National Yang Ming Chiao Tung University
|
| P2-56 (221) | EDA & Testing |
An Application-Oriented Design Space Exploration Framework for Digital Compute-in-Memory Systems
National Central University
|
| P2-57 (230) | EDA & Testing |
Stage-Aware Layout–Mask–Contour Modeling for Learning-Based Lithography Prediction
National Chung Hsing University
|
| P2-58 (252) | EDA & Testing |
SPICE Model for Dynamic Electro-Thermal Modeling and Short-Circuit Failure Analysis of 650V SiC MOSFETs
National Taiwan University
|
| P2-59 (274) | EDA & Testing |
A Robust LLM-Assisted System for Gate-Level Netlist Analysis and Transformation
Yuan Ze University
|
