Session 1

Advanced Sensor Array Integrated Circuits

8月5日 (三) 10:50–12:00 國際廳 1, 2F Analog & RF

場次主席

江建學, 國立雲林科技大學

洪振傑, 逢甲大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S1-1 (55)	10:50–11:07	A 0.8-V 8T2C PWM Frame-Difference Vision Sensor with Ramp-Domain Background Calibration for Multimode Processing-in-Sensor Applications Yu-Hsiang Wang, Yi-Jhen Chen and Chih-Cheng Hsieh National Tsing Hua University
S1-2 (65)	11:07–11:24	A Motion-Adaptive Edge-Extraction Image Sensor with Dynamic Detection and Static Edge Persistence Si-Xuan Wang, Man-Tzu Wu, Yu-Jung Tseng, John Carl Joel Salao Marquez, and Chih-Cheng Hsieh National Tsing Hua University
S1-3 (36)	11:24–11:41	A Frame-Differencing CMOS Image Sensor for >120-dB Temporal Event Detection Dynamic Range Using Pixel-Grouped Multiple Exposure John Carl Joel Salao Marquez and Chih-Cheng Hsieh National Tsing Hua University
S1-4 (47)	11:41–11:58	System Integrated Chip Design of a SPAD Sensor Array with High-Precision Time-to-Digital Converter Circuit Tian Yuan-An, Don-Gey Liu, and Ching-Hwa Cheng Feng Chia University

Session 2

Nyquist-rate ADC

8月5日 (三) 10:50–12:00 國際廳 2, 2F Analog & RF

場次主席

陳信良, 淡江大學

陳信樹, 國立臺灣大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S2-1 (74)	10:50–11:07	An 84dB-SNDR 16-bit 2-MS/s Capacitor-Calibration SAR ADC in 80-nm CMOS Zhe-Yuan Kuo, Yu-Xian Huang, and Yung-Hui Chung National Taiwan University of Science and Technology
S2-2 (180)	11:07–11:24	A 12-bit 400-MS/s Pipelined-SAR ADC Using an Adaptively Biased Floating Inverter Amplifier and Miller Negative Capacitance Gain Correction Chia-Han Wu, Ming-Yi Huang, and Kuang-Wei Cheng National Cheng Kung University
S2-3 (89)	11:24–11:41	A Two-Channel Time-Interleaved 1.28 GS/s 8.6-bit Hybrid SAR/TDC ADC With a Dual-Mode Comparator and PWM-Based VTC Yu-Hsiang Huang and Chih-Cheng Hsieh National Tsing Hua University
S2-4 (122)	11:41–11:58	A 10-b 56-MS/s Calibration-Free SAR ADC Array for Touch Sensing Applications Chin-Wei Cheng, Xing-Rong Lee, and Soon-Jyh Chang National Cheng Kung University

Session 3

Signal Processing Architectures for Communication and Intelligent Systems

8月5日 (三) 10:50–12:00 國際廳 3, 2F Digital & System

場次主席

沈中安, 國立臺灣科技大學

賴以威, 國立臺灣師範大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S3-1 (136)	10:50–11:07	A High-Throughput Massive MU-MIMO RSMA Detector for Next-Gen Communication Systems Po-Jen Chen, Ren-Hao Chiou, and Chia-Hsiang Yang National Taiwan University
S3-2 (77)	11:07–11:24	A Soft-Output MMSE Detector Based on Modified Refinement Jacobi Method for 128×32 Massive MIMO Systems Chih-Feng Wu1, Chi-Kay Huang2, Muh-Tian Shiue2, Hung-Hsiang Huang1, and Ya-Chu Chang1 1Chang Gung University 2National Central University
S3-3 (164)	11:24–11:41	Frequency Domain Equalization Design for Gigabit Automotive Ethernet System Chih-Feng Wu1, Muh-Tian Shiue2, Yu-Jun Chen2, Min-Yuan Tsai1, and Tong-Da Lee1 1Chang Gung University 2National Central University
S3-4 (170)	11:41–11:58	Dual-Side Sparse Accelerator with Timestep Packing for MSF-Based Spiking YOLOX Tzu-Yu Huang and Pei-Jun Lee National Taiwan University of Science and Technology

Session 4

Quantization and Numerical Optimization for LLM and VLM

8月5日 (三) 10:50–12:00 湖光廳 2, 2F Digital & System

場次主席

黃柏蒼, 國立陽明交通大學

黃郁惠, 國立中央大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S4-1 (288)	10:50–11:07	Low-Bit Hadamard Rotation for Hardware-Efficient LLM Quantization Yin-Jui Chang and Yun-Nan Chang National Sun Yat-sen University
S4-2 (219)	11:07–11:24	Outlier-Aware Mixed PoT/CSD Activation Quantization for Hardware-Efficient Vision-Language Model Inference Yen-Chen Chen1, Chia-Yun Chiang1, Hui-Yun Deng1, and Yu-Hui Huang2 1Yuan Ze University 2National Central University
S4-3 (92)	11:24–11:41	TQIR: Trellis Quantization with INT-Reconstruction for Large Language Models Kuang-Ting Huang and Tian-Sheuan Chang National Yang Ming Chiao Tung University
S4-4 (195)	11:41–11:58	A Precision-Preserving and LUT-Efficient Softmax Architecture for MX-Based LLM Accelerators Meng-Hsun Hsieh, Cheng-Zong Li, and Juinn-Dar Huang National Yang Ming Chiao Tung University

Session 5

Trustworthy and resilient hardware testing and security

8月5日 (三) 10:50–12:00 湖光廳 3, 2F EDA & Testing

場次主席

黃俊郎, 國立臺灣大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S5-1 (182)	10:50–11:07	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis Chi-Jui Hsieh1, Charles H.-P. Wen1, Kai-Chiang Wu1, Hsuan-Ming Huang2, Chun-Chieh Wu2, Yen-Ju Su1, and Wei-Ren Chen1 1National Yang Ming Chiao Tung University 2Mediatek Inc.
S5-2 (155)	11:07–11:24	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops Lowry P.-T. Wang, Hao-Chi Lin, Charles H.-P. Wen, and Herming Chiueh National Yang Ming Chiao Tung University
S5-3 (168)	11:24–11:41	Attack-Guided Refinement of MUX Key-Gate Candidates for Oracle-Less Logic Locking Bo-Hao Huang1, Yung-Chih Chen1, and Wang-Dao Tseng2 1National Taiwan University of Science and Technology 2Yuan Ze University
S5-4 (176)	11:41–11:58	Gate-Level Hardware Trojan Detection via Structural Analysis and Graph Neural Networks Che-Yuan Liu, Yen-Jung Chen, Keng-Chia Liang, and Yu-Guang Chen National Central University

Session 6

Advances in placement and legalization

8月5日 (三) 10:50–12:00 湖光廳 5+6, 2F EDA & Testing

場次主席

林榮彬, 元智大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S6-1 (171)	10:50–11:07	Learning Connectivity-Aware Reward Modeling for PPA-Realistic Macro Placement Jai-Ming Lin, Zong-Ze Lee, and Wei-Hao Huang National Cheng Kung University
S6-2 (71)	11:07–11:24	Hybrid-Region-Aware Multi-Electrostatic Placement with Resistive-Force Stabilization Jai-Ming Lin1, Hung-Wei Hsu1, Tan Huang1, Chen-Fa Tsai2, De-Shiun Fu2, and Shih-Cheng Huang2 1National Cheng Kung University 2Global Unichip Corporation
S6-3 (19)	11:24–11:41	Standard-Cell-Aware Learning-Guided Adaptive Weighting for Analytical Mixed-Size Placement Cheng-Yu Chiang1, Wei-Hsiang Tseng1, Yao-Wen Chang1, and Hung-Ming Chen2 1National Taiwan University 2National Yang Ming Chiao Tung University
S6-4 (242)	11:41–11:58	Timing and Power Co-Optimization in FinFlex Legalization with Cell Version Substitution Da-Wei Huang and Shao-Yun Fang National Taiwan University of Science and Technology

Session 7

Clock Generation and Biomedical Circuits

8月5日 (三) 13:30–15:00 國際廳 1, 2F Analog & RF

場次主席

邱茂菱, 國立臺灣科技大學

林鴻文, 元智大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S7-1 (42)	13:30–13:47	A 96 dB Input Dynamic Range Galvanic Skin Response Readout IC with 3.5 pArms Input-Referred Noise for Mental Stress Monitoring Lin Chou1, Yi-Jie Lin1, Kun-Ju Tsai2, and Yu-Te Liao1 1National Yang Ming Chiao Tung University 2Industrial Technology Research Institute
S7-2 (110)	13:47–14:04	A Programmable DLL-based Delay Chain with an Auto-calibration Technique Hsuan-Cheng Liu, Jun-Yu Chen, Wen-Qi Liu and Jen-Chieh Liu National United University
S7-3 (178)	14:04–14:21	A Dual-Mode Wound-Care Stimulator With 0.738-mV Residual Voltage Using Pulse-Width Adaptive Charge Balancing Yi-Man Fang, Lin Chou, Chia-Chen Hsieh, Li-Chia Tai, Wei-Chen Huang, Tsung-Heng Tsai, and Yu-Te Liao National Yang Ming Chiao Tung University
S7-4 (159)	14:21–14:38	A 3.76-GHz Fast-Locking Sub-Sampling PLL with Frequency Detection Handoff Circuit and Dynamic Charge-Pump Jin-An Liu, Hsing-Hua Yen, Tian-Lin Zhang, and Kuo-Hsing Cheng National Central University
S7-5 (199)	14:38–14:55	A Spur-Reduction Technique for Sub-Sampling PLLs Using Dummy-Load QSSPD in 16nm FinFET Yu-Lung Lo and Jyun-Si Lin National Kaohsiung Normal University

Session 8

High-Resolution ADCs and DACs

8月5日 (三) 13:30–15:00 國際廳 2, 2F Analog & RF

場次主席

魏嘉玲, 國立成功大學

陳信良, 淡江大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S8-1 (7)	13:30–13:47	A 101.8-dB SNDR Discrete-Time Dynamic Zoom ADC Using Two-Stage Floating Inverter Amplifier in 180-nm CMOS Chun-Yang Chiu, Yi-Jing Lee, and Yung-Hui Chung National Taiwan University of Science and Technology
S8-2 (189)	13:47–14:04	A 12-bit 16-GS/s RF DAC with Hybrid Current Switches achieving > 32dBc SFDR in 16nm FinFET Pin-Chen Shih, Le-An Chen, Tang-Wei Chen, Po-Sheng Chang, Ching-Che Chang, An-Chi Tsai, and Chia-Hung Chen National Yang Ming Chiao Tung University
S8-3 (121)	14:04–14:21	A 103.14-dB SNDR 106.04-dB DR hybrid sturdy MASH-21 DSM for audio applications Jung-Yu WU, Chun-Chen Liao, and Chia-Yu Yao National Taiwan University of Science and Technology
S8-4 (196)	14:21–14:38	AI-Assisted Hierarchical Optimization and Validation of a Fourth-Order Noise-Shaping SAR ADC Chien-Hung Kuo, Hao-Cheng Hsu, Jui-Cheng Chen, Chun-Hsien Chiang, Yu-Si Chen, and Tzu-Chi Huang National Taiwan Normal University
S8-5 (115)	14:38–14:55	A 13-bit 5-MS/s SAR ADC Utilizing Dual-Mode Linearity-Improvement Schemes Chia-Liang Lai, Yu-Xian Huang, and Yung-Hui Chung National Taiwan University of Science and Technology

Session 9

Low-Power Arithmetic Circuits and Hardware Security

8月5日 (三) 13:30–15:00 國際廳 3, 2F Digital & System

場次主席

施信毓, 國立中山大學

沈中安, 國立臺灣科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S9-1 (76)	13:30–13:47	A 460.8-Gb/s 81.2-fJ/bit All-Digital Hyperchaotic TRNG Chip with In-Memory Entropy Source Yu-Shuo Chang, Cheng-Bin Chen, and Yuan-Hao Huang National Tsing Hua University
S9-2 (226)	13:47–14:04	A Fully Parallel Stochastic 3D Ising Machine with Level-Wise Bitstream Scheduling Yu-Hsin Kuo, Chi-En Chen, and Kun-Chih Chen National Yang Ming Chiao Tung University
S9-3 (3)	14:04–14:21	Efficient CKKS Key-Switching Accelerator Design via Adaptive Special Modulus Selection and Approximate Basis Conversion Qi-Xian Wu, Tsu-Hsiung Huang, Yun-Ting Hsu, and Ming-Der Shieh National Cheng Kung University
S9-4 (116)	14:21–14:38	Parametric Hardware Architecture Design for HQC-128 Post-Quantum Cryptosystem Chung-Ming Chang, Zi-Yin Chen, and Shiann-Rong Kuang National Sun Yat-sen University
S9-5 (263)	14:38–14:55	Adaptive Vision Transformer Accelerator with Memory-Aware Tiled-Streaming Architecture for Reduced On-Chip Memory Overhead Chen-Ming Lee1,2, I-Chyn Wey1, and Tee Hui Teo2 1Chang Gung University 2Singapore University of Technology and Design

Session 10

Hardware Accelerators for Emerging Neural Models

8月5日 (三) 13:30–15:00 湖光廳 2, 2F Digital & System

場次主席

蔡家齊, 國立成功大學

林承鴻, 國立臺灣師範大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S10-1 (215)	13:30–13:47	Hybrid Hardware Accelerator Supporting Multi-Scale Convolutional Neural Networks and Large Language Model Architectures Chung-Bin Wu, Chih-Peng Fan, Ying-Chieh Chen, Hu-Yi Tang, Yu-Chen Hsu, and Ying-Chieh Lin National Chung Hsing University
S10-2 (202)	13:47–14:04	Design and Implementation of On-Device Learning for Ternary-Weight Transformers Pei-Han Lin and Tzi-Dar Chiueh National Taiwan University
S10-3 (262)	14:04–14:21	An MX-Block Friendly Multi-precision Accelerator for Edge LLM Inference Yu-Ren Jou, Lu-Ying Jen, and Tian-Sheuan Chang National Yang Ming Chiao Tung University
S10-4 (225)	14:21–14:38	MAMBA-NoC: A NoC-Based Mamba Accelerator with a Hardware-Efficient Piecewise-Linear Activation Unit Cheng-En (Shawn) Hsieh and Kun-Chih (Jimmy) Chen National Yang Ming Chiao Tung University
S10-5 (85)	14:38–14:55	SliceLGN: Hardware-Software Co-Design for Parallel Inference of Class-Partitioned Logic Gate Networks Sheng-Fa Hou and Shanq-Jang Ruan National Taiwan University of Science and Technology

Session 11

Emerging Technologies and Applications

8月5日 (三) 13:30–15:00 湖光廳 3, 2F Emerging Technologies

場次主席

黃朝宗, 國立清華大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S11-1 (146)	13:30–13:47	A 6.94-TOPS/W Channel Estimation Processor for Edge-AI Hybrid RIS Communications Shu-Yu Lin, Ting-Hsuan Chien, Jung-Chun Chi, and Yuan-Hao Huang National Tsing Hua University
S11-2 (191)	13:47–14:04	Quantum SMT Solver for Bit-Vector Theory Lei-Han Yao1,2, Li-Jung Chen1, Si-Han Chen1, Yean-Ru Chen1, and Shang-Wei Lin2 1National Cheng Kung University 2Singapore Institute of Technology
S11-3 (124)	14:04–14:21	CNN-Based Edge Computing System for Real-Time Ruminal Methane Monitoring Chin-Cheng Wu1, Jin-Chern Chiou2, Yi-Chich Chiu1, Chung-Yen Chuang1, and Yu-Hsuan Shen1 1National Ilan University 2National Yang Ming Chiao Tung University
S11-4 (286)	14:21–14:38	Intelligent Active Infrared Rodent Activity Event Detection System with Power-Saving Sleep Mode Shin-Chi Lai1, Kuan-Lin Liu2, Kuo-Cheng Tseng1, Ying-Hsiu Hung1, Szu-Ting Wang3, and Wei-Da Chen2 1National Formosa University 2National Yunlin University of Science and Technology 3Chaoyang University of Technology
S11-5 (193)	14:38–14:55	Quantangle-SAT: A Quantum SAT Solver Based on Entanglement and Equivalence Checking Ji-Qing YAN1, Shang-Wei LIN2, Yu-Chung CHEN1, and Yean-Ru CHEN1 1National Cheng Kung University 2Singapore Institute of Technology

Session 12

Advanced packaging and PCB design automation

8月5日 (三) 13:30–15:00 湖光廳 5+6, 2F EDA & Testing

場次主席

林忠緯, 國立臺灣大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S12-1 (94)	13:30–13:47	High-Speed Advanced Package Substrate Routing with Plated-Through-Hole-Aware Optimization Che-Wu Yeh1, Shao-Hsiang Chen1, Po-Jen Lin1, Yao-Wen Chang1,2, Hsin-Ying Lin2, Huang-Yu Chen2, and Jim Chang2 1National Taiwan University 2Taiwan Semiconductor Manufacturing Company
S12-2 (238)	13:47–14:04	An Agile Three Stage RDL Routing Acceleration Framework for Advanced Packaging Design Space Exploration Zi-Xian Tang, Cheng-Ning Wang, Yi-Hao Huang, and Yi-Yu Liu National Taiwan University of Science and Technology
S12-3 (107)	14:04–14:21	Physics-Informed Branch-and-Cut for Analytical Concurrent Decoupling Capacitor Placement in PCB Power Distribution Networks Zong-Ying Cai and Yao-Wen Chang National Taiwan University
S12-4 (207)	14:21–14:38	Reinforcement Learning-based P/G Plane Synthesis for Power Via Maximization in Multilayer RDLs Shang-Che Lee and Mark Po-Hung Lin National Yang Ming Chiao Tung University
S12-5 (254)	14:38–14:55	LLM-based Early-Stage Overcurrent Protection Verification in PCB Design Pei-Hsin Kang, Cheng-Yi Lu, Chun-Ning Huang, and Mark Po-Hung Lin National Yang Ming Chiao Tung University

Session 13

Power Management IC I: Digital Control Techniques

8月5日 (三) 16:20–17:15 國際廳 1, 2F Analog & RF

場次主席

陳柏宏, 國立陽明交通大學

許益捷, 國立臺灣海洋大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S13-1 (275)	16:20–16:37	Digital Peak Current Mode Buck Converter using Current Estimation and Calibration Techniques Shang-Chien Yang, Jian-Hsu Lu, and Chien-Hung Tsai National Cheng Kung University
S13-2 (169)	16:37–16:54	A 14-bit, 125ps Temporal Resolution, CMOS Multi-Phase Dual Edge Digital Pulse Width Modulator Ying-Yu Yang, Wei-Chih Wang, Yen-Yu Chen, Yi-Ting Lin, and Yu-Te Liao National Yang Ming Chiao Tung University
S13-3 (43)	16:54–17:11	Digital Pulse Width Modulator Based on Carry Chain Design Yi-Hua Wang and Pao-Lung Chen National Kaohsiung University of Science and Technology

Session 14

Wireline Transceiver

8月5日 (三) 16:20–17:15 國際廳 2, 2F Analog & RF

場次主席

彭朋瑞, 國立清華大學

翁峻鴻, 國立雲林科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S14-1 (41)	16:20–16:37	A 1.01-pJ/b, 4-Gb/s Receiver for NAND Flash Memory Interface with Source Cross-Coupled CTLE and 1-Tap Time-Based Speculative DFE Shiang-Yuan Li1, Hsuan-Chieh Lin1, Yu-Jia Chen1, Ping-Hsuan Hsieh1, Shang-Chi Yang2, Su-Chueh Lo2, Jiansyu Lin2, Chun-Hao Tsai2, Tung-Yu Li2, Ken-Hui Chen2, and Chun-Hsiung Hung2 1National Tsing Hua University 2Macronix International Co., Ltd
S14-2 (248)	16:37–16:54	A 0.44-pJ/b, 12-Gb/s Unmatched Receiver for NAND Flash Memory with Wide-Range De-skew and Instant-Toggling ILRO Yu-Jia Chen1, Ping-Hsuan Hsieh1, Shang-Chi Yang2, and Su-Chueh Lo2 1National Tsing Hua University 2Macronix International Co., Ltd
S14-3 (259)	16:54–17:11	A 56-Gb/s Feed-Forward Equalized Simultaneous Bi-Directional Die-to-Die Transceiver Shao-Chun Chuang, Yang Su, Ping-Heng Wu and Ching-Yuan Yang National Chung Hsing University

Session 15

Secure and Reliable Architectures for Multi-Core, Network-on-Chip, and SoC Systems

8月5日 (三) 16:20–17:15 國際廳 3, 2F Digital & System

場次主席

張雲南, 國立中山大學

劉宗德, 國立臺灣大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S15-1 (228)	16:20–16:37	Bit-Optimal Trajectory Path Encoding for Anonymous Routing in NoC-based Systems Jyun-Nian Chang, Hsuan-Yu Huang, Dai-Ling Chen, and Kun-Chih Chen National Yang Ming Chiao Tung University
S15-2 (56)	16:37–16:54	Fault Tolerance for DQN-Based Chiplet System Applications Li-Lun Kuo, Yu-Cheng Chen, Chu-En Chang, Guan-Lun Chen, and Chun-Lung Hsu National Central University
S15-3 (21)	16:54–17:11	MMIO and RoCC Integrations of a CORDIC Accelerator on a RISC-V Rocket Chip SoC Chien-Wei Liao, Wenn-Yi Lin, Hsin-Yi Chan, Kuan-Hsuan Tung, and Chung-An Shen National Taiwan University of Science and Technology

Session 16

In-Memory Search and Computing in Memory

8月5日 (三) 16:20–17:15 湖光廳 2, 2F Digital & System

場次主席

謝易叡, 國立陽明交通大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S16-1 (4)	16:20–16:37	A 1.6GHz High In-Memory-Search Throughput, High Energy Efficiency, Hybrid Segmented Computation with Pre-charge-Free In-Memory-Search TCAM Yun Kai Yeh1,2, Qi Hua Lin2, Wei Chih Ho2, Chia Wei Su2, I Chyn Wey2, Tee Hui Teo1, and An Yeu Wu3 1Singapore University of Technology and Design 2Chang Gung University 3National Taiwan University
S16-2 (102)	16:37–16:54	A Multi-Function SRAM Macro Supporting In-Memory Computing and In-Memory Search for Linear and Lookup-Based Operations Chia-Wei Su1, An-Yeu (Andy) Wu2, and I-Chyn Wey1 1Chang Gung University 2National Taiwan University
S16-3 (46)	16:54–17:11	High Energy Efficiency TCAM In-Memory Search Architecture with Pre-Determined Short-Circuit Current Cutoff Wei-Chieh Lee2, Chen-Ming Lee2, Chia-Wei Su1, Chun-Fu Chen4, I-Chieh Hsu1, I-Chyn Wey1, Tee Hui Teo2, and An-Yeu (Andy) Wu3 1Chang Gung University, Taiwan 2Singapore University of Technology and Design 3National Taiwan University 4National Taiwan University of Science and Technology

Session 17

Circuits & Systems for Visual Signal Processing

8月5日 (三) 16:20–17:15 湖光廳 3, 2F Digital & System

場次主席

蔡佩芸, 國立臺灣大學

范志鵬, 國立中興大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S17-1 (244)	16:20–16:37	An Energy-Efficient Tensor Display Processor for 3D Virtual Reality Ching-Yen Lee, Yueh-Feng Tsai, Ying-Sheng Lin, and Chia-Hsiang Yang National Taiwan University
S17-2 (35)	16:37–16:54	A Low-Latency Low-Light Image Enhancement VLSI Architecture for Edge Devices Chih-Jen Chen, Achmad Arif Bryantono, Tsu-Hsiang Chen, and Chi-Chia Sun National Taipei University
S17-3 (145)	16:54–17:11	Design and Implementation of a Baseball Toss Batting Training System Using a 6-Axis Manipulator Po-Chen Lee, Ruei-Chi Yang, and Hsi-Pin Ma National Tsing Hua University

Session 18

AI for Test and Test for AI

8月5日 (三) 16:20–17:15 湖光廳 5+6, 2F EDA & Testing

場次主席

許舒涵, 國立成功大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S18-1 (187)	16:20–16:37	Easily Testable and BIST Techniques for SRAM-Based Compute-In-Memory Systems Shyue-Kung Lu and Chin-Jung Lee National Taiwan University of Science and Technology
S18-2 (135)	16:37–16:54	Deep Learning-Based Anomaly Detection for Circuit Waveform Testing Wei-Che Chang, Hao-Ming Hsu, Kai-Hsiang Chang, Chia-Hsun Lee, Hung-Wei Hsueh, Ching-Wei Tseng, and Shu-Han Hsu National Cheng Kung University
S18-3 (233)	16:54–17:11	Wafer-Zone-Based Vmin Prediction for Adaptive Test Li-Yang Wang1, Ming-Ze Hsu1, Shang-Ting Lin1, James Chien-Mo Li1, Harry H. Chen2, LinChien Chen2, Joy Tsai2, and Chingting Lin2 1National Taiwan University 2MediaTek Inc.

Session 19

Power Management IC II: Analog Control Techniques

8月6日 (四) 10:50–12:00 國際廳 1, 2F Analog & RF

場次主席

王三輔, 國立勤益科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S19-1 (86)	10:50–11:07	Overlap-Free Interleaved PWM and Precision-Timed Active Bootstrap in a Sub-1-V to 15-V Hybrid Boost Converter for PMUTs Li-Lun Hsu and Shuenn-Yuh Lee National Cheng Kung University
S19-2 (24)	11:07–11:24	A High-Efficiency P-SSHI Rectifier with Active Diode and SBB for Self-Powered UAV Sensing Systems Wan-Ju Li, Shao-Ku Kao, Wen-Shuo Chang, and Yu-Hsuan Lee Chang Gung University
S19-3 (216)	11:24–11:41	A Constant-On-Time-Controlled Buck Converter with Capacitor Current Sensing and Body-Diode Conduction Sensing Techniques Ching-Wei Zhan1, Yuh-Shyan Hwang1, and Dong-Shiuh Wu2 1National Taipei University of Technology 2Lunghwa University of Science and Technology
S19-4 (243)	11:41–11:58	A Pseudo-Constant-Frequency Buck Converter with Optimum On-Time Control and Virtual-Inductor-Current Compensation Techniques Wei-Li Lin1, Yuh-Shyan Hwang1, and Dong-Shiuh Wu2 1National Taipei University of Technology 2Lunghwa University of Science and Technology

Session 20

Wireless Transceiver

8月6日 (四) 10:50–12:00 國際廳 2, 2F Analog & RF

場次主席

張鴻埜, 國立中央大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S20-1 (87)	10:50–11:07	A 204.8-GHz OOK Transmitter Supporting High-Speed Operation with Integrated Dielectric Resonator Antenna in 40-nm CMOS Hsuan-Ping Shen and Chun-Hsing Li National Taiwan University
S20-2 (181)	11:07–11:24	A 2.4 GHz 0.2 V 55 μW Class-D VCO with Dual-Transformer-Coupled Resonator Shao-Chen Chang, Yuan-Jung Chen, and Kuang-Wei Cheng National Cheng Kung University
S20-3 (179)	11:24–11:41	A Low-Power Sub-Harmonic Mixer-First Receiver Using Capacitive Stacking and Cascaded Windmill-Divider LO Generation Kuo-Ching Tai, Ren-De Huang, and Kuang-Wei Cheng National Cheng Kung University
S20-4 (192)	11:41–11:58	An 80-Mb/s Multichannel Injection-Locked BPOOK/QPSK Ultra-Low-Power Transmitter Zhi-Wei Lin, Yu-Ting Cheng, and Kuang-Wei Cheng National Cheng Kung University

Session 21

Low-Power Arithmetic Circuits and Hardware Security

8月6日 (四) 10:50–12:00 湖光廳 3, 2F Digital & System

場次主席

魏一勤, 長庚大學

沈中安, 國立臺灣科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S21-1 (279)	10:50–11:07	Design of a 2-GHz CORDIC-Based NCO and Digital IQ Modulator for Qubit Control Pin-Syuan Lu and Hsiao-Chin Chen National Taiwan University of Science and Technology
S21-2 (6)	11:07–11:24	FPGA Implementation of Randomness-Driven Qubit Generation for Quantum Key Distribution Systems Yen-Lun Lai, Han-Jang Chen, and Hsi-Pin Ma National Tsing Hua University
S21-3 (45)	11:24–11:41	A 100%-Reliable Digital RO-PUF with BCH(16,8) Error Correction in 90nm CMOS Yi-Ting Yen and Chi-Chia Sun National Taipei University
S21-4 (95)	11:41–11:58	Built-In Self-Test and Built-In Self-Calibration for FPGA Digital Pulse Width Modulation based on Pulse Shrinking Poki Chen, Yao-Ting Chen, Yu-Hsien Wu, Yu-Chieh Fan, and Tai-Sen Lin National Taiwan University of Science and Technology

Session 22

Intelligent Computing for Biomedical and Edge Applications

8月6日 (四) 10:50–12:00 湖光廳 2, 2F Digital & System

場次主席

宋啟嘉, 國立臺北大學

鍾菁哲, 國立中正大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S22-1 (161)	10:50–11:07	A Programmable Two-Layer ADC-Less Analog Gated Recurrent Unit Accelerator for Sensor-Edge ECG Intelligent Computing Huai-Jiun Chin1, Yu-Feng Lin1, Hsuan-Wei Pu1, Yun-Ming Hsu1, Chun-Yen Huang2, Liang Chang2, and Sheng-Yu Peng2 1National Taiwan University of Science and Technology 2National Yang Ming Chiao Tung University
S22-2 (78)	11:07–11:24	An Embedded Flash-Based Analog Gated Recurrent Unit for Sensor Edge Intelligent Computing Chun-Yen Huang1, Hsuan-Wei Pu2, Kai-Fong Chen1, Huai-Jiun Chin2, and Sheng-Yu Peng1 1National Yang Ming Chiao Tung University 2National Taiwan University of Science and Technology
S22-3 (82)	11:24–11:41	An Energy-Efficient Deep Learning Accelerator for ECG and PCG Signal Classifications Ming-Han Tsai1, Shuenn-Yuh Lee1, and Ju-Yi Chen2 1National Cheng Kung University 2National Cheng Kung University Hospital
S22-4 (64)	11:41–11:58	Design and Implementation of a Millisecond-Scale Meat Grinder Protection System: FPGA Prototyping with Lightweight Edge AI and a Reconfigurable CNN Accelerator Yi-Ting Sun, Yu-Shan Zhang, Shou-Yi Fei, Kuan-Hsi Chen, and Yu-Guang Chen National Central University

Session 23

Circuits & Systems for Speech and Biomedical Signal Processing

8月6日 (四) 10:50–12:00 湖光廳 3, 2F Digital & System

場次主席

賴信志, 國立虎尾科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S23-1 (229)	10:50–11:07	A Resource-Efficient 23×53 Mixed-Radix FFT Processor for Real-Time Speech Recognition Wei-Da Chen and Guan-Ting Pan National Yunlin University of Science and Technology
S23-2 (38)	11:07–11:24	A Hardware-Oriented Compact CNN with Squared-L2 Distance Inference for OCT Screening Pin-Han Wen1, Yue Fang Kuo1, and Cheng-Hung Lin2 1Yuan Ze University 2National Taiwan Normal University
S23-3 (281)	11:24–11:41	A Time-Frequency Bidirectional LSTM Architecture with Dynamic Frequency-Domain Preprocessing for ECG Arrhythmia Classification Shin-Chi Lai1,2, Yao-Feng Liang1, and Szu-Ting Wang2 1National Formosa University 2Chaoyang University of Technology
S23-4 (83)	11:41–11:58	A Low-SRAM Fully Streaming Accelerator for Real-Time Speech Enhancement Hsuan-Jung Lai and Shanq-Jang Ruan National Taiwan University of Science and Technology

Session 24

Multiphysics aware design optimization

8月6日 (四) 10:50–12:00 湖光廳 5+6, 2F EDA & Testing

場次主席

林柏宏, 國立陽明交通大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S24-1 (125)	10:50–11:07	A Two-Phase Guided MCTS Framework for Carbon- and Aging-Aware Task Scheduling Yin-Rong Zhuo1, Chun-Yen Chu1, Yu-Guang Chen1, and Ing-Chao Lin2 1National Central University 2National Yang Ming Chiao Tung University
S24-2 (69)	11:07–11:24	Integrated PDN and Placement Co-Optimization for Global and Local IR-Drop Mitigation Jai-Ming Lin1, Pin-Yu Chen1, Zhao-Xian Huang1, Chen-Fa Tsai2, De-Shiun Fu2, and Shih-Cheng Huang2 1National Cheng Kung University 2Global Unichip Corporation
S24-3 (144)	11:24–11:41	ThPA-GPU: A GPU Acceleration Framework for ThPA Chia-Yu Lin and Yu-Min Lee National Yang Ming Chiao Tung University
S24-4 (185)	11:41–11:58	TSV-Aware Fourier Neural Operator-Based Thermal Prediction for 3D IC Floorplan Optimization Bing-Chen Li1, Shao-Yu Wu1, Yu-Xiang Lin1, Chen-Yu Hsu1, James Chien-Mo Li1, Norman Chang2, Akhilesh Kumar2, Ying-Shiun Li2, and Lang Lin2 1National Taiwan University 2Synopsys Inc.

Session 25

CDR and Power Management

8月7日 (五) 10:30–11:40 國際廳 1, 2F Analog & RF

場次主席

郭柏佑, 國立雲林科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S25-1 (217)	10:30–10:47	Self-Adjusting Gate Driver for Crosstalk Suppression in SiC MOSFETs Jian-Bang Hou1, Wei-Bang Su1, Kuan-Chia Chen1, Hsu-An Li2, and Chung-Hsun Huang2 1National Chung Cheng University 2National Cheng Kung University
S25-2 (90)	10:47–11:04	FPGA-Controlled Master-Slave Interleaved BCM Boost PFC Converter With Phase Identification and 0.93% Current-Balance Accuracy Chih-Lin Chiu, Yi-Chen Jian, Chun-Yen Chiu and Chien-Hung Tsai National Cheng Kung University
S25-3 (37)	11:04–11:21	A 0.9-3.6 Gb/s PVT Insensitive and Adaptive Loop Bandwidth CDR with 100 kHz ±10% SSC Modulation Depth and Ground Bounce Tolerant for Intra-Panel Interface Sung Huang and Soon-Jyh Chang National Cheng Kung University
S25-4 (173)	11:21–11:38	A 2.2-7 Gb/s 1/5-Rate CDR Circuit with ±7% SSC Tracking and Fast Acquisition Jia-Zhe Liao and Soon-Jyh Chang National Cheng Kung University

Session 26

Intelligent Edge Computing and Timing Function

8月7日 (五) 10:30–11:40 國際廳 2, 2F Analog & RF Digital & System EDA & Testing

場次主席

賴信志, 國立虎尾科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S26-1 (48)	10:30–10:47	Low-Power CNN Inference Engine for AIoT Edge Sensing: Algorithm-Hardware Co-Design with Full Digital IC Implementation Flow Ching-Ting Chiu National Taiwan Normal University
S26-2 (246)	10:47–11:04	An FPGA-based Agricultural Robot Design for Crop Status Warning Applications Jun-Hao Zhang, Hung-Yu Lin, and Chun-Hsian Huang National Changhua University of Education
S26-3 (50)	11:04–11:21	A 10 GHz FMCW PLL for 150 ns Chirp Duration, 5.68 GHz/μs Chirping Rate with Background Frequency Calibration Chih-Chieh Li and Wei-Zen Chen National Yang Ming Chiao Tung University
S26-4 (234)	11:21–11:38	Machine-Learning-Based Prediction for Programming Clock Generator for DVFS Applications Ming-Ze Hsu1, Shang-Ting Lin1, Li-Yang Wang1, James Chien-Mo Li1, Harry H. Chen2, LinChien Chen2, Joy Tsai2, and Chingting Lin2 1National Taiwan University 2MediaTek Inc.

Session 27

Secure and Reliable Architectures for Multi-Core, Network-on-Chip, and SoC Systems

8月7日 (五) 10:30–11:40 湖光廳 3, 2F Digital & System

場次主席

沈中安, 國立臺灣科技大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S27-1 (127)	10:30–10:47	A Low-Latency FPGA Architecture for Multi-Customer Repeated-IOC Strategies and Real-Time Risk Control Guan-Cheng Liao, Bo-Yu Jhuang, Kuan-Hsi Chen, Chuan-Chieh Kao, Shin-Kai Tzou and Hsi-Pin Ma National Tsing Hua University
S27-2 (177)	10:47–11:04	An NI-Based Dynamic Defense Against Black Hole Router Attacks in Network-on-Chip You-Kai Xu and Shih-Hsu Huang Chung Yuan Christian University
S27-3 (81)	11:04–11:21	A Framework for Run-Time Trojan Horse Detection Using Cross Auditing Cheng-Yuan Tseng1, Shi-Yu Huang1, and Chi-Kang Chen2 1National Tsing Hua University 2Taiwan Electronic System Design Automation
S27-4 (213)	11:21–11:38	Group-Shuffled Arithmetic Masking: A Hardware-Efficient Hybrid Countermeasure Against CPA on Edge CNN Accelerators Yi-Lin Chen1 and Cheng-Hung Lin2 1Yuan Ze University 2National Taiwan Normal University

Session 28

Energy-Efficient CNN/DNN Accelerators for Edge Inference

8月7日 (五) 10:30–11:40 湖光廳 2, 2F Digital & System

場次主席

黃郁惠, 國立中央大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S28-1 (61)	10:30–10:47	Statistical Error-Balanced Decomposed MAC Architecture with Heterogeneous Approximation for Energy Efficient and Timing-Resilient CNN Accelerators Wei-Ji Chao, Chu-Cheng Chen and Tong-Yu Hsieh National Sun Yat-sen University
S28-2 (231)	10:47–11:04	RO-ResNet: A Frequency-aware Adversarially Robust Octave Convolution ResNet Accelerator Ya-Chi Peng, Chao-Wei Chang, Kang-Lun Fong, Yun-Hao Yang, and An-Yeu (Andy) Wu National Taiwan University
S28-3 (166)	11:04–11:21	PPACC: A Pattern-Aware DNN Accelerator with Compute-in-Compressed Dataflow on FPGA Pei-Xuan Huang, Yi-Shuo Hung, Po-Han Chen, and Chia-Chi Tsai National Cheng Kung University
S28-4 (204)	11:21–11:38	Lightweight Convolutional Neural Network for Tooth Identification and FPGA Hardware Implementation Chung-Bin Wu, Ying-Shan Lin, Hu-Yi Tang, Yu-Chen Hsu, and Ying-Chieh Lin National Chung Hsing University

Session 29

Specialized Computing Architectures and Design Methodologies

8月7日 (五) 10:30–11:40 湖光廳 3, 2F Digital & System

場次主席

陳坤志, 國立陽明交通大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S29-1 (63)	10:30–10:47	A 3D NAND Flash CIM Architecture for Efficient Long-Read Genome Alignment Tsan-Jen Chen1 and Ing-Chao Lin2 1National Cheng Kung University 2National Yang Ming Chiao Tung University
S29-2 (139)	10:47–11:04	bANS: A Bit-Plane Tabled Asymmetric Numeral Systems Architecture For Resource-Constrained Edge Device Chi-Chang Lin and Chih-Hung Kuo National Cheng Kung University
S29-3 (224)	11:04–11:21	Hardware-Equivalent Design-Space Evaluation of Data Augmentation and Quantization for Edge FPGA AI Systems I-An Lin, Hsu-Cheng Chen, and Wei-Jyun Chen National United University
S29-4 (157)	11:21–11:38	An 8-to-12 GHz All-Digital PLL for DDR SDRAM Registering Clock Driver Shuo-Lin Tseng and Wei-Zen Chen National Yang Ming Chiao Tung University

Session 30

AI-driven design analysis and optimization

8月7日 (五) 10:30–11:40 湖光廳 5+6, 2F EDA & Testing

場次主席

麥偉基, 國立清華大學

發表編號	發表時間	論文標題 / 作者 / 所屬學校/公司
S30-1 (282)	10:30–10:47	ROUTING-AWARE EARLY FLOORPLANNING VIA GNN-SEEDED SIMULATED ANNEALING Shao-Yu Wei, Hung-Ying Chu, Tzu-Wei Huang, Chi-Huang Chiang, Wang-Dauh Tseng, Yu-Cheng Lin, and Rung-Bin Lin Yuan Ze University
S30-2 (153)	10:47–11:04	MCTS Meets AllSAT: A Scalable Framework for Simultaneously Optimizing Standard Cell PPA Yen-Ju Su, Jun-Wei Yu, Chi-An Lin, Aaron C.-W. Liang, Han-Ya Tsai, and Charles H.-P. Wen National Yang Ming Chiao Tung University
S30-3 (27)	11:04–11:21	Physics-Guided Neural Networks Integrated with gm/ID and Genetic Algorithm for Automated Analog Circuit Sizing Yu-Hsuan Lee, Shao-Ku Kao, Wen-Shuo Chang and Wan-Ju Li Chang Gung University
S30-4 (23)	11:21–11:38	Risk-Driven IC Defect Classification with VLM Guidance Hua-Tai Chang, Hao-Chiang Shao, Shao-Yun Fang, Yan-Hsiu Liu, and Chia-Wen Lin National Yunlin University of Science and Technology